Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Thus, controlling short channel effects is important to assuring proper semiconductor operation.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacers.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. Manufacturing is more difficult because the vertical dimensions associated with the depths of source/drain junctions and the thin extensions to the source/drain junctions must be decreased in a ratio corresponding to the reduction in lateral dimension of the manufactured MOSFET. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 or 40 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation, diffusion doping and activation techniques make transistors on the IC susceptible to a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
As MOSFET scaling continues to be reduced, ultra-shallow and highly-activated junctions are essential for device performance. Source/Drain (S/D) extensions shallower than 30 nm are needed for sub-70 nm CMOS transistors. In addition, the transition from the S/D extensions to the channel region (laterally) must be as precipitous as possible. An aggressive scaling of the lateral abruptness of S/D extensions is critical for controlling short-channel effects in a sub-100 nm CMOS transistor. On the other hand, external resistances (S/D extension, contact, etc.) play a significant role in the device performance.
Along with the aggressive scaling of S/D extension junction depth and abruptness, it may be desirable to form a more highly doped S/D extension, as devices become smaller. For example, a Super-Doped Extension (SDE), instead of the extension associated with conventional design of LDD (lightly doped drain) or HDD (highly doped drain), are desired as transistors become smaller. Dopant electrical activation in the SDE becomes a great challenge.
Another result of the minimization of transistor critical dimensions is that the total thermal budget (Dt) of the drain and source regions and the semiconductor gate becomes more critical. In general, the thermal budget for dopant activation in the source/drain junction (including source/drain extension) should be as low as possible to provide good formation of an ultra-shallow junction. Fundamentally, reducing the thermal budget has several advantages including: (1) more accurate formation of ultra-shallow junctions; (2) formation of ultra-tight dope profiles, such as, profiles for halo implants or retrograded channel implants; and (3) reduction of dopant penetration through the gate oxide and into the gate (e.g., Boron (B) in P-channel MOSFETs). Both shallow source and drain extensions and tight profile pocket regions help to improve the immunity of a transistor to short-channel effects.
Taking advantage of the results attainable via a lower thermal budget, conventional processes have reduced thermal budgets for CMOS transistor fabrication by utilizing a rapid thermal annealing (RTA) to heat the substrate. RTA does not require a significant period of time to heat the substrate. Another approach involves a spike RTA which increases the ramping rate of RTA. Nonetheless, the substrate must be exposed to the RTA for a time period of one second or more to appropriately diffuse and activate dopants.
Conventional rapid thermal anneal processes, such as RTA, face the problems of undesired thermal diffusion and low electrical activation limited by solid solubility. One possible solution is to use a laser thermal process (LTP). LTP includes advantages such as: 1) "zero" thermal budget (a laser pulse is a few nanoseconds, approximately 8 orders of magnitude shorter than rapid thermal processes and the thermal diffusion is almost negligible); 2) metastable process above dopant solid solubility limit, allowing active dopant concentrations larger than 10.sup.21 cm.sup.- to be achieved; and 3) selective local heating of specific regions of silicon does not add thermal budget to Vth/channel/halo implant profiles.
One of the major integration issues of LTP is that the poly-Si line above the field oxide (e.g., shallow trench isolation region) could over-melt due to poor thermal dissipation through the thick oxide. This over-melting can cause the polysilicon line to be deformed or disconnected.
Thus, there is a need for a process which overcomes these problems, such as, over-melting due to poor thermal dissipation through thick oxide. Further, there is a need for a transistor fabrication method which avoids problems of thermal diffusion and low electrical activation occurring in conventional rapid thermal processes. Even further still, there is a need for a transistor which is manufactured by a selective laser anneal process which uses a highly reflective mask.